| DC Field | Value | Language |
|---|
| dc.contributor.author | Sosnowski, J. | |
| dc.date.accessioned | 2020-03-26T10:57:10Z | - |
| dc.date.available | 2020-03-26T10:57:10Z | - |
| dc.date.created | 2001-03-27 | |
| dc.date.issued | 2001-03-27 | |
| dc.identifier.citation | Sosnowski J. Path delay fault coverage in pseudorandom test sequences / J. Sosnowski // Вісник Національного університету “Львівська політехніка”. — Львів : Видавництво Національного університету “Львівська політехніка”, 2002. — № 440 : Радіоелектроніка та телекомунікації. — С. 26–32. | |
| dc.identifier.uri | https://ena.lpnu.ua/handle/ntb/47902 | - |
| dc.format.extent | 26-32 | |
| dc.language.iso | en | |
| dc.publisher | Видавництво Національного університету “Львівська політехніка” | |
| dc.relation.ispartof | Вісник Національного університету “Львівська політехніка”, 440 : Радіоелектроніка та телекомунікації, 2002 | |
| dc.title | Path delay fault coverage in pseudorandom test sequences | |
| dc.type | Article | |
| dc.rights.holder | © Національний університет “Львівська політехніка”, 2002 | |
| dc.rights.holder | © Sosnowski J., 2002 | |
| dc.contributor.affiliation | Warsaw University of Technology | |
| dc.format.pages | 7 | |
| dc.identifier.citationen | Sosnowski J. Path delay fault coverage in pseudorandom test sequences / J. Sosnowski // Visnyk Natsionalnoho universytetu "Lvivska politekhnika". — Lviv : Vydavnytstvo Natsionalnoho universytetu "Lvivska politekhnika", 2002. — No 440 : Radioelektronika ta telekomunikatsii. — P. 26–32. | |
| dc.relation.references | 1. R. C. Aitken, Nanometer technology effects on fault models for 1C testing IEEE Computer, November 1999, pp.46-51. | |
| dc.relation.references | 2. D. Bhattarcharya, P. Agrawal, V D. AgraWal, Test generation for path delay faults using binary decision diagrams, IEEE Transaction on Computers, vol.44, no.3L March, 1995, pp.434-447. | |
| dc.relation.references | 3. C-A. Chen, S. K, Gupta, Design o f efficient BIST test pattern generators for delay testings IEEE Transactions on Computer Aided Design o f Integrated Circuits and Systems, vol.15, no. 12, Dec. 1996, pp. 1568-1575. | |
| dc.relation.references | 4. R. David, Random testing of digital circuits, Marcel Dekker Inc., New York, 1998. | |
| dc.relation.references | 5. K. Fuchs, F. Fink; MH. Schulltz, Dynamite: an efficient automatic test pattern generation system for path delay faults, IEEE Transactions on Computer-Aided Design, vol.10, no. 10, October, 1991, pp.1323-1335. | |
| dc.relation.references | 6. D. Kagaris, S. Tragoudas, D. Karayiannis, Improved nonenumerative path delay fault coverage based on optimal polynomial time algorithms, IEEE Transactions on Computer Aided Design o f Integrated Circuits and Systems, vol 16, no.3, 1997, pp.309-315, | |
| dc.relation.references | 7. I. Pomeranz, S.M. Reddy, On achieving complete coverage of delay faults in full scan circuits using locally available lines, Proceedings of IEEE International Test Conference, 1999, pp.923-931. | |
| dc.relation.references | 8. C. P. Ralikumar, A. Mittal, Hierarchical delay fault simulation, Proceedings of 12th IEEE International Conference on VLSI Design, 1999, pp. 635-639. | |
| dc.relation.references | 9. J. Savir, W. McAnney, Random pattern testability o f delay faultst IEEE Transactions on Computers, vol.37, no. 3L March, 1998, pp.291-300. | |
| dc.relation.references | 10. J. Savir, Skewed-load transition test: part 1 and part 2, Proceedings o f IEEE Int: Test Conference, 1999, pp. 705-722. | |
| dc.relation.references | 11. J. Sosnowski, T. Wabia, T. Bech, Pathy delay fault testability andlisis, Proc. of IEEE Int Symposium on Defect and Fault Tolerance, 2000, pp.338-346. | |
| dc.relation.references | 12. U. Sparmann, D. Luxenburger, et ah, Fast identification o f robust dependent path delay faults^Proceedings of 32nd Design Automation Conference, IEEE Computer Society, 1995, pp. 119-125. | |
| dc.relation.references | 13. S. Tragoudas, Accurate path delay fault coverage is feasible, Proceedings o f IEEE International Test Conference, 1999, pp.201-210. | |
| dc.relation.references | 14. S. Underwood, WO. Law, S. K'ahg, H. Konuk, Fastpath: a path delay test test generator for standard scan designs, Proceedings o f IEEE Int. Test Conference, 1999, pp. 154-163. | |
| dc.relation.references | 15. P. Varma, On path delay testing in a standard scan environment, Proceedings o f IEEE Int. Test Conference, 1999, pp.164-173. | |
| dc.relation.references | 16. Scope Logic Products, Application and Data Manual, Texas Instruments, 1996. | |
| dc.relation.referencesen | 1. R. C. Aitken, Nanometer technology effects on fault models for 1C testing IEEE Computer, November 1999, pp.46-51. | |
| dc.relation.referencesen | 2. D. Bhattarcharya, P. Agrawal, V D. AgraWal, Test generation for path delay faults using binary decision diagrams, IEEE Transaction on Computers, vol.44, no.3L March, 1995, pp.434-447. | |
| dc.relation.referencesen | 3. C-A. Chen, S. K, Gupta, Design o f efficient BIST test pattern generators for delay testings IEEE Transactions on Computer Aided Design o f Integrated Circuits and Systems, vol.15, no. 12, Dec. 1996, pp. 1568-1575. | |
| dc.relation.referencesen | 4. R. David, Random testing of digital circuits, Marcel Dekker Inc., New York, 1998. | |
| dc.relation.referencesen | 5. K. Fuchs, F. Fink; MH. Schulltz, Dynamite: an efficient automatic test pattern generation system for path delay faults, IEEE Transactions on Computer-Aided Design, vol.10, no. 10, October, 1991, pp.1323-1335. | |
| dc.relation.referencesen | 6. D. Kagaris, S. Tragoudas, D. Karayiannis, Improved nonenumerative path delay fault coverage based on optimal polynomial time algorithms, IEEE Transactions on Computer Aided Design o f Integrated Circuits and Systems, vol 16, no.3, 1997, pp.309-315, | |
| dc.relation.referencesen | 7. I. Pomeranz, S.M. Reddy, On achieving complete coverage of delay faults in full scan circuits using locally available lines, Proceedings of IEEE International Test Conference, 1999, pp.923-931. | |
| dc.relation.referencesen | 8. C. P. Ralikumar, A. Mittal, Hierarchical delay fault simulation, Proceedings of 12th IEEE International Conference on VLSI Design, 1999, pp. 635-639. | |
| dc.relation.referencesen | 9. J. Savir, W. McAnney, Random pattern testability o f delay faultst IEEE Transactions on Computers, vol.37, no. 3L March, 1998, pp.291-300. | |
| dc.relation.referencesen | 10. J. Savir, Skewed-load transition test: part 1 and part 2, Proceedings o f IEEE Int: Test Conference, 1999, pp. 705-722. | |
| dc.relation.referencesen | 11. J. Sosnowski, T. Wabia, T. Bech, Pathy delay fault testability andlisis, Proc. of IEEE Int Symposium on Defect and Fault Tolerance, 2000, pp.338-346. | |
| dc.relation.referencesen | 12. U. Sparmann, D. Luxenburger, et ah, Fast identification o f robust dependent path delay faults^Proceedings of 32nd Design Automation Conference, IEEE Computer Society, 1995, pp. 119-125. | |
| dc.relation.referencesen | 13. S. Tragoudas, Accurate path delay fault coverage is feasible, Proceedings o f IEEE International Test Conference, 1999, pp.201-210. | |
| dc.relation.referencesen | 14. S. Underwood, WO. Law, S. K'ahg, H. Konuk, Fastpath: a path delay test test generator for standard scan designs, Proceedings o f IEEE Int. Test Conference, 1999, pp. 154-163. | |
| dc.relation.referencesen | 15. P. Varma, On path delay testing in a standard scan environment, Proceedings o f IEEE Int. Test Conference, 1999, pp.164-173. | |
| dc.relation.referencesen | 16. Scope Logic Products, Application and Data Manual, Texas Instruments, 1996. | |
| dc.citation.journalTitle | Вісник Національного університету “Львівська політехніка” | |
| dc.citation.issue | 440 : Радіоелектроніка та телекомунікації | |
| dc.citation.spage | 26 | |
| dc.citation.epage | 32 | |
| dc.coverage.placename | Львів | |
| dc.coverage.placename | Lviv | |
| dc.subject.udc | YДK 612.396 | |
| Appears in Collections: | Радіоелектроніка та телекомунікації. – 2002. – №440
|
