Програмно-апаратна реалізація цифрового пристрою фазового автоматичного підстроювання частоти

Abstract

Описано створену програмно-апаратну реалізацію цифрового пристрою фазового автоматичного підстроювання частоти (ЦФАПЧ). Досліджено процес схоплення частоти гармонічного коливання. Наведено графіки ключових сигналів пристрою ЦФАПЧ і здійснено їх порівняння з результатами дослідження імітаційної моделі ЦФАПЧ. This article is devoted to the creation of a firmware implementation of the digital phaselocked loop (DPLL). DPLLs are more perspective than analog PLLs in terms of reliability and technical characteristics. Moreover, DPLLs potentially have better noise immunity than analog ones. Advantage of the firmware implementation of the DPLL is its flexibility in configuration. So, the creation of such implementation gives a possibility to speed up further investigation of DPLL noise immunity. The article describes the block diagram of the DPLL and explains its principle of operation. Furthermore, this article presents mathematical models of all building blocks of the DPLL, including their transfer functions and difference equations. In addition, there are deducted the formulas for digital filter coefficients on the basis of a location of poles and zeros of the DPLL transfer function. The block diagram of hardware part of the DPLL implementation is also presented. It is built on STM microcontroller and a PC (personal computer), which is connected to it in order to collect data during an operation of the DPLL. The algorithm of software part of the DPLL implementation is depicted in this paper as well. In order to prove an ability of work of created firmware implementation the frequency acquisition process of harmonic oscillation is investigated. The paper shows diagrams of DPLL key signals. Experimental results were collected and compared with investigation results of existing simulation model of this DPLL. Their comparison demonstrates full accordance of experimental (firmware) and simulation models of the DPLL.